pnp silicon epitaxial transistor this pnp silicon epitaxial transistor is designed for use in low voltage, high current applications. the device is housed in the sot-223 package, which is designed for medium power surface mount applications. ? high current: i c = 1.0 amp ? the sot-223 package can be soldered using wave or reflow. ? sot-223 package ensures level mounting, resulting in improved thermal conduction, and allows visual inspection of soldered joints. the formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die. ? available in 12 mm tape and reel use bcp69t1 to order the 7 inch/1000 unit reel. use bcp69t3 to order the 13 inch/4000 unit reel. ? npn complement is bcp68 maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit collector-emitter voltage v ceo 25 vdc collector-base voltage v cbo 20 vdc emitter-base voltage v ebo 5.0 vdc collector current i c 1.0 adc total power dissipation @ t a = 25 c (1) derate above 25 c p d 1.5 12 watts mw/ c operating and storage temperature range t j , t stg 65 to 150 c 1. device mounted on a glass epoxy printed circuit board 1.575 in. x 1.575 in. x 0.059 in.; mounting pad for the collector lead min. 0.93 sq. in. device marking ce thermal characteristics characteristic symbol max unit thermal resistance e junction-to-ambient (surface mounted) r q ja 83.3 c/w lead temperature for soldering, 0.0625 from case time in solder bath t l 260 10 c sec electrical characteristics (t a = 25 c unless otherwise noted) characteristics symbol min typ max unit off characteristics collector-emitter breakdown voltage (i c = 100 m adc, i e = 0) v (br)ces 25 e e vdc collector-emitter breakdown voltage (i c = 1.0 madc, i b = 0) v (br)ceo 20 e e vdc emitter-base breakdown voltage (i e = 10 m adc, i c = 0) v (br)ebo 5.0 e e vdc on semiconductor november, 2001 rev. 4 1 publication order number: bcp69t1/d bcp69t1 medium power pnp silicon high current transistor surface mount on semiconductor preferred device case 318e-04, style 1 to-261aa 1 2 3 4 collector 2,4 base 1 emitter 3 preferred devices are recommended choices for future use and best overall value.
bcp69t1 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristics unit max typ min symbol off characteristics collector-base cutoff current (v cb = 25 vdc, i e = 0) i cbo e e 10 m adc emitter-base cutoff current (v eb = 5.0 vdc, i c = 0) i ebo e e 10 m adc on characteristics dc current gain (i c = 5.0 madc, v ce = 10 vdc) (i c = 500 madc, v ce = 1.0 vdc) (i c = 1.0 adc, v ce = 1.0 vdc) h fe 50 85 60 e e e e 375 e e collector-emitter saturation voltage (i c = 1.0 adc, i b = 100 madc) v ce(sat) e e 0.5 vdc base-emitter on voltage (i c = 1.0 adc, v ce = 1.0 vdc) v be(on) e e 1.0 vdc dynamic characteristics current-gain e bandwidth product (i c = 10 madc, v ce = 5.0 vdc) f t e 60 e mhz figure 1. typical electrical characteristics 200 100 70 20 -10 -100 -1000 i c , collector current (ma) figure 1. dc current gain i c , collector current (ma) f , current gain bandwidth product (mhz) t figure 2. current gain bandwidth product 300 200 100 30 70 i c , collector current (ma) v, voltage (volts) figure 3. saturation and aono voltages 0 160 0 v r , reverse voltage (volts) figure 4. capacitances c, capacitance (pf) 50 h fe , current gain v ce = -1.0 v t j = 25 c 50 -10 -100 -1000 v ce = -10 v t j = 25 c f = 30 mhz -1.0 -0.8 -0.6 -0.4 -0.2 -1.0 -100 -1000 -10 v (be)sat @ i c /i b = 10 t j = 25 c v (be)on @ v ce = -1.0 v v (ce)sat @ i c /i b = 10 120 80 40 c ob c ib -5.0 -1.0 -2.0 -4.0 -2.5 -5.0 c ib cob t j = 25 c -1.0 -2.0 -1.5 -3.0
bcp69t1 http://onsemi.com 3 p d = t j(max) t a r q ja p d = 150 c 25 c 83.3 c/w = 1.50 watts ? the soldering temperature and time should not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient should be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. information for using the sot223 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection sot223 power dissipation the power dissipation of the sot223 is a function of the pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . us- ing the values provided on the data sheet for the sot223 package, p d can be calculated as follows. the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 1.5 watts. the 83.3 c/w assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 1.5 watts. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, a higher power dissipation of 1.6 watts can be achieved using the same footprint. interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference should be a maximum of 10 c. 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 mm inches 0.091 2.3 sot223
bcp69t1 http://onsemi.com 4 package dimensions case 318e04 issue k sot223 (to261) h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. style 1: pin 1. base 2. collector 3. emitter 4. collector on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. bcp69t1/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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